Clock Stop - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

The Clock Stop goes High when the clock is flat-lined for more than 10 clock cycles. Once the clock is stale for 10 or more clock cycles, it initiates the calculation to detect the stop and signals the clock_stop High. The clock stop signal will not become high immediately and can take up to 256 clock cycles from the time the clock is flat. This calculation requires a set of reference clock cycle periods, time at which the clock_stop will go High depends on the ratio of user_clk and ref_clk .