The following table gives the duty cycle values which are possible with the divide values from 1 to 8. Each clock must fall under any one of the divide and duty cycle combinations to satisfy condition 1.
|
In_freq / Out<1-4>_freq |
Out<1-4>_Duty_Cycle |
|---|---|
|
1,2,4,6,8 |
50% |
|
3 |
33% - 34% |
|
5 |
40% |
|
7 |
42% -43% |
Condition 2
Condition 2 is satisfied when you select any one of the following buffers for all the output clocks:
1. Buffer
2. Buffer_with_CE
3. BUFGCE_DIV