Core Architecture - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

The Clocking Wizard generates source code HDL to implement a clocking network. The generated clocking network typically consists of a clocking primitive (MMCM(E2/E3) _ADV or PLL(E2/E3) _ADV ) plus some additional circuitry which typically includes buffers and clock pins. The network is divided into segments as illustrated in This Figure . Details of these segments are described in the following sections.

Figure 3-12: Provided Clocking Network

X-Ref Target - Figure 3-12