Dynamic Reconfiguration through AXI4-Lite - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

The Clocking Wizard core provides an AXI4-Lite interface for the dynamic reconfiguration of the clocking primitive MMCM/PLL. This interface is enabled when Dynamic Reconfig is enabled and the selected interface is AXI4-Lite . This feature is not supported when Spread Spectrum is enabled. Mixed-language RTL is delivered by the core when the AXI4-Lite interface is used. To reconfigure the phase and duty cycle, select Phase Duty Cycle Config . Enabling this option utilizes DSP resources. By default, this option is deselected to optimize the design for area. Resource utilization for the AXI4-Lite interface configuration of the Clocking Wizard IP core using Kintex®-7 part xc7k325t is described in Table: Kintex-7 FPGA Resource Utilization with AXI4-Lite Interface .

Table 4-1: Kintex-7 FPGA Resource Utilization with AXI4-Lite Interface

Site Type

Used when Phase Duty Cycle Config = FALSE

Used when Phase Duty Cycle Config = TRUE

Slice LUTs



Slice Registers






This Figure provides details of the signals of AXI4-Lite and Table: Clock Configuration Registers provides details of the clock configuration registers.

The Clocking Wizard core uses a configuration state machine listed in MMCM and PLL Dynamic Reconfiguration (XAPP888) [Ref 6] and extends from two fixed-state configurations to program any valid range of Multiply, Divide, Phase and Duty Cycle. In this state machine, state 1 corresponds to default state configured through the Clocking Wizard interface. State 2 corresponds to the user configuration loaded into the Clock Configuration Register detailed in Table: Clock Configuration Registers . State 2 values are also initialized with the state 1 values so that a valid configuration is stored by default. All the dynamic reconfiguration registers are to be updated whenever you want to reprogram the clock.

Dynamic Reconfiguration uses resources for internal calculations in the wizard. The user provides CLKFBOUTMULT, DIVCLK_DIVIDE, CLKOUTxPHASE, and CLKOUTx_DUTY other user understandable parameters. They cannot be directly mapped to MMCM/PLL DRP registers. User understandable attributes are converted to MMCM DRP registers and written into primitive. This calculation is done in the wizard using few function call and makes the wizard utilize the resources mentioned in MMCM and PLL Dynamic Reconfiguration (XAPP888) [Ref 6] .

If the phase duty cycle configuration parameter is not enabled, the wizard only calls functions related to frequency. This option must be enabled to change phase and duty cycle dynamically. Next, wizard calls the functions related to phase and duty cycle at the cost of resources. If resources cannot be used, use wizard to call these functions during IP generation and write a different address set containing direct DRP data. Here wizard does not do any calculations, it guides the user with the value needed to be written into the registers. Write DRP must be selected to enable this feature.

To do a dynamic reconfiguration, follow the below steps:

1. Write all the Clock Configuration Registers, and then check for the status register.

2. Before writing into the C_BASEADDR + 0x200 register detailed in Table: Kintex-7 FPGA Resource Utilization with AXI4-Lite Interface , make sure that these values result in a valid VCO frequency range of MMCM/PLL which is calculated using the following equation:

VCO Frequency = (Input Clock Frequency) * (CLKFBOUT_MULT)/DIVCLK_DIVIDE

For details on the VCO range, refer to the DC and Switching Characteristics section of the applicable device data sheet.

3. If the status register value is 0x1, start the reconfiguration by writing Clock Configuration Register 23 with 0x3.

CAUTION! The fractional enable bit in Clock Configuration Register 0 must only be enabled if the value of the clock FBOUT MULT is a non-integer. Similarly, the fractional enable bit in Clock Configuration Register 2 must only be enabled if the value of CLKOUT0_DIVISE is a non-integer.