Example 1: All Seven Clocks Active with MMCM as Primitive - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)
Document ID
PG065
Release Date
2022-04-20
Version
6.0 English
Table 3-5: Example 1 Configuration

Clock

Frequency (MHz)

Duty Cycle

clk_out2

300 (= clk_out1/2)

50

clk_out3

200 (= clk_out1/3)

33.33

clk_out4

150 (= clk_out1/4)

50

clk_out5

120 (= clk_out1/5)

40

clk_out6

100 (= clk_out1/6)

50

clk_out7

100 (= clk_out1/6)

50

Figure 3-1: Example 1 Configuration

X-Ref Target - Figure 3-1

Figure_3-1.png

1. Optimize clock structure not enabled:

° The resource tab shows one MMCM, one IBUFG, and seven BUFG.

° The clocking structure is as follows (which is non-optimal):

Figure 3-2: Optimize Clock Structure Not Enabled

X-Ref Target - Figure 3-2

Figure_3-2.png

° The summary table is as follows:

Figure 3-3: Summary Table for Optimize Clock Structure Not Enabled

X-Ref Target - Figure 3-3

Figure_3-3.png

2. Optimize clock structure enabled:

° The resource tab is updated immediately after enabling optimized clocking structure:

Figure 3-4: Optimize Clock Structure Enabled

X-Ref Target - Figure 3-4

Figure_3-4.png

° The clocking structure is as follows:

Figure 3-5: Clocking Structure for Optimize Clock Structure Enabled

X-Ref Target - Figure 3-5

Figure_3-5.png

° The summary table is as follows:

Figure 3-6: Summary Table for Optimize Clock Structure Enabled

X-Ref Target - Figure 3-6

Figure_3-6.png