Example 2: Both Clocks Active with PLL as Primitive - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)
Document ID
PG065
Release Date
2022-04-20
Version
6.0 English
Table 3-6: Example 2 Configuration

Clock

Frequency (MHz)

Duty Cycle

clk_out2

300 (= clk_out1/2)

50

1. Optimize clock structure not enabled:

° The resource tab shows one PLL, one IBUFG, and two BUFGs.

° The summary table is updated as follows:

Figure 3-7: Summary Table for Optimize Clock Structure Not Enabled

X-Ref Target - Figure 3-7

Figure_3-7.png

° The clocking structure is as follows:

Figure 3-8: Clocking Structure for Optimize Clock Structure Not Enabled

X-Ref Target - Figure 3-8

Figure_3-8.png

2. Optimize clock structure enabled:

° The resource tab shows one PLL, one IBUFG, one BUFG, and one BUFGCE_DIV.

° The summary table is updated as follows:

Figure 3-9: Summary Table for Optimize Clock Structure Enabled

X-Ref Target - Figure 3-9

Figure_3-9.png

° The clocking structure is as follows:

Figure 3-10: Clocking Structure for Optimize Clock Structure Enabled

X-Ref Target - Figure 3-10

Figure_3-10.png