Example Design - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

The following file describes the example design for the Clocking Wizard core.



The top-level example designs adds clock buffers where appropriate to all of the input and output clocks. All generated clocks drive counters, and the High bits of each of the counters are routed to a pin. This allows the entire design to be synthesized and implemented in a target device to provide post place-and-route gate-level simulation.

Note: Example design files are delivered only in Verilog.