Example for Dynamic Reconfiguration through AXI4-Lite - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

Note: For Clocking Wizard v5.2 and earlier, you need to write 0x00000007 followed by 0x00000002 into Clock Configuration Register 23, to consolidate the redundant bits that the IP has upgraded. Now you can initiate the transaction by writing 0x00000003 to the clock configuration register 23, but the backward compatibility still exists.

The input and output clock frequencies are 100 MHz in the Clocking Wizard by default.

1. Configure Clock Configuration Register 0 (Address: C_BASEADDR + 0x200) with 0x00000A01. Writing this value sets DIVCLK_DIVIDE value to 1 and CLKFBOUT_MULT to 10.

2. Configure Clock Configuration Register 2 (Address: C_BASEADDR + 0x208) with 0x00000005. Writing this value sets CLKOUT0_DIVIDE to 5. The VCO frequency being 1000 MHz, dividing it by CLKOUT0_DIVIDE gives the 200 MHz frequency on the clkout1 in the IP. Check for the status register; if the status register value is 0x1, then go to step 3.

3. Configure Clock Configuration Register 23 (Address: C_BASEADDR + 0x25C) with 0x00000003 to set the LOAD and SEN bits.

4. Wait for the locked signal. The new frequency can be checked at the clkout1 output port.

Note: You can reset to the default settings by configuring the Clock Configuration Register 23 (Address: C_BASEADDR + 0x25C) with the value 0x00000001.

Refer to Example Design for more details.