• The selection of mixed-mode clock manager (MMCM) and phase-locked loop (PLL) primitives. Integrated design environment (IDE) options are enabled for the supported features for the primitives.
• The Safe Clock Startup feature enables a stable and valid clock at the output. Enabling the Sequencing feature provides sequenced output clocks.
• Accepts up to two input clocks and up to seven output clocks per clock network.
• Provides an AXI4-Lite interface for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
• Automatically configures a clocking primitive based on the selected clocking features.
• Automatically calculates the voltage-controlled oscillator (VCO) frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements.
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
UltraScale+™ families, UltraScale™ families, Zynq ® -7000 SoC, 7 Series |
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Supported User Interfaces |
AXI4-Lite |
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Resources |
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Special Features |
PLL(E2/E3/E4), MMCM(E2/E3/E4), Spread Spectrum Clocking |
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Provided with Core |
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Design Files |
Verilog (2) |
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Example Design |
Verilog |
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Test Bench |
Verilog (2) |
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Constraints File |
.xdc (Xilinx Design Constraints) |
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Simulation Model |
For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
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Instantiation Template |
Verilog and VHDL Wrapper |
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Supported
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Not Applicable |
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Tested Design Flows |
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Design Entry Tools |
Vivado ® Design Suite |
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Simulation |
Mentor Graphics Questa Advanced Simulator , Vivado Simulator |
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Synthesis Tools |
Synplify PRO E-2012.03, Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54102 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP Catalog. 2. The top RTL design file is delivered in Verilog and the sub-modules can still be in VHDL or Verilog. 3. A standalone C example can be found in the Vitis directory (<install_directory>/data/embeddedsw/XilinxProcessorIPLib/ drivers/clk_wiz_vx_x). Linux OS and driver support information is available from the Xilinx Wiki page . Common clock Linux driver information for Zynq UltraScale+ MPSoCs is available from the Common Clock Framework Wiki page .
4.
For the supported versions of third-party tools, see the
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