Features - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

Document ID
Release Date
6.0 English

The selection of mixed-mode clock manager (MMCM) and phase-locked loop (PLL) primitives. Integrated design environment (IDE) options are enabled for the supported features for the primitives.

The Safe Clock Startup feature enables a stable and valid clock at the output. Enabling the Sequencing feature provides sequenced output clocks.

Accepts up to two input clocks and up to seven output clocks per clock network.

Provides an AXI4-Lite interface for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle.

Automatically configures a clocking primitive based on the selected clocking features.

Automatically calculates the voltage-controlled oscillator (VCO) frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements.

LogiCORE IP Facts Table

Core Specifics

Supported Device Family (1)

UltraScale+™ families, UltraScale™ families, Zynq ® -7000 SoC, 7 Series

Supported User Interfaces



Performance and Resource Utilization web page .

Special Features

PLL(E2/E3/E4), MMCM(E2/E3/E4), Spread Spectrum Clocking

Provided with Core

Design Files

Verilog (2)

Example Design


Test Bench

Verilog (2)

Constraints File

.xdc (Xilinx Design Constraints)

Simulation Model

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Instantiation Template

Verilog and VHDL Wrapper

S/W Driver

Not Applicable

Tested Design Flows

Design Entry Tools

Vivado ® Design Suite


Mentor Graphics Questa Advanced Simulator , Vivado Simulator

Synthesis Tools

Synplify PRO E-2012.03, Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: 54102

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page


1. For a complete listing of supported devices, see the Vivado IP Catalog.

2. The top RTL design file is delivered in Verilog and the sub-modules can still be in VHDL or Verilog.

3. A standalone C example can be found in the Vitis directory (<install_directory>/data/embeddedsw/XilinxProcessorIPLib/ drivers/clk_wiz_vx_x). Linux OS and driver support information is available from the Xilinx Wiki page . Common clock Linux driver information for Zynq UltraScale+ MPSoCs is available from the Common Clock Framework Wiki page .

4. For the supported versions of third-party tools, see the
Xilinx Design Tools: Release Notes Guide .