MMCM Counter Cascading - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

The CLKOUT6 divider (counter) can be cascaded with the CLKOUT4 divider. This provides the capability of an output divider that is larger than 128. The CLKOUT6 counter feeds the input of the CLKOUT4 divider. There is a static phase offset between the output of the cascaded divider and all other output dividers. You need to select CLKOUT4_CASCADE option to use this feature. If you are using this option, you need to use the override mode to generate all the required frequencies.

CLKFBOUT_USE_FINE_PS is a variant of the CLKFBOUT counter that enables fine phase shifting for CLKFBOUT . Select the Dynamic Phase Shift option to use fine phase shifting for CLKFBOUT .

You can only select the STARTUP_WAIT option in the Override mode, that works with the Configuration CLK_Cycle option, to wait for the Clock Manager to lock before completing the startup sequence.

See 7 Series FPGAs Clocking Resources User Guide (UG472) [Ref 9] and UltraScale Architecture Clocking Resources User Guide (UG572) [Ref 8] for more information.

The generated source code contains the input and output clock summaries shown in the next summary page, as shown in This Figure .

Figure 4-11: Primitive Override Screen (Spread Spectrum Unselected)

X-Ref Target - Figure 4-11

Figure 4-12: Primitive Override Screen (Spread Spectrum Selected)

X-Ref Target - Figure 4-12