Matched Routing - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

Enabling matched routing on the clocks conveys the information to the implementation tool to use the same CLOCK_ROOT for the selected clocks. This is performed by setting the CLOCK_DELAY_GROUP property on the corresponding clock nets in the Xilinx® design constraints (XDC) file for the IP.

For clocks without matched routing, the clock skew on timing paths with other clocks is not optimized. This can lead to difficult timing closure. Use matched routing preferably for high-frequency clocks with many clock domain crossing paths.

The Wizard infers the BUFGCE_DIV as buffer when matched routing is selected. This buffer helps in better matched routing.