Overview - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

This chapter introduces the Clocking Wizard core and provides related information, including recommended design experience, additional resources, technical support, and ways of submitting feedback to Xilinx. The Clocking Wizard core generates source register transfer level (RTL) code to implement a clocking network matched to your requirements. Both Verilog and VHDL design environments are supported.