The Wizard allows you to name the ports according to their needs. If you want to name the HDL port for primary clock input, type the port name in the adjacent text box. The text boxes contain the default names. In the case of the primary clock input, the default name is CLK_IN1 .
IMPORTANT: Be careful when changing the port names, as it could result in syntax errors if the port name entered is any reserved word of VHDL or Verilog, or if that signal is already declared in the module.