Table: Clock Configuration Registers shows the set of registers applicable when the Dynamic Reconfiguration mode is selected. All registers are accessed as 32-bit.
|
Base Address + Offset (hex) |
Register Name |
Reset Value (hex) |
Access Type |
Description |
|---|---|---|---|---|
|
C_BASEADDR + 0x00 |
Software Reset Register (SRR) |
N/A |
W (1) |
Software Reset Register To activate software reset, the value 0x0000_000A must be written to the register. Any other access, read or write, has undefined results. |
|
C_BASEADDR + 0x04 |
Status Register (SR) |
0x00000000 |
R |
Status Register Bit[0] = Locked When 1 MMCM/PLL is Locked and ready for reconfiguration. The status of this bit is 0 during reconfiguration. |
|
C_BASEADDR +0x08 |
Clock Monitor Error Status Register |
0x00000000 |
R |
This register gives the error status bits of the clock monitor feature. |
|
C_BASEADDR +0x0C |
Interrupt Status |
0x00000000 |
R/W |
Interrupt Status for Clock Stop, Clock Overrun, and Clock Underrun. These bits are gated by Interrupt enable bits. Interrupts corresponding to the enabled bits in Interrupt enable register would be updated in this register. |
|
C_BASEADDR +0x10 |
Interrupt Enable |
0x00000000 |
R/W |
Interrupt Enable for Clock Stop, Clock Overrun, and Clock Underrun bits in the Interrupt status register. |
|
Dynamic Reconfiguration Registers |
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|
C_BASEADDR + 0x200 |
Clock Configuration Register 0 |
Default (2) : 0x01010A00 |
R/W |
Bit[7:0] = DIVCLK_DIVIDE Eight bit divide value applied to all output clocks. Bit[15:8] = CLKFBOUT_MULT Integer part of multiplier value i.e. For 8.125, this value is 8 = 0x8. Bit[25:16] = CLKFBOUT_FRAC Multiply (3) Fractional part of multiplier value i.e. For 8.125, this value is 125 = 0x7D. Note: You need not set any bit for specifying that the multiplier value is fractional. Just mention the fractional value in the register space. The value of CLKFBOUT fractional divide can be from 0 to 875 representing the fractional multiplied by 1000. |
|
C_BASEADDR + 0x204 |
Clock Configuration Register 1 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKFBOUT_PHASE Phase values entered are Signed Number for +/- phase. |
|
C_BASEADDR + 0x208 |
Clock Configuration Register 2 |
Default (2) : 0x0004000a |
R/W |
Bit[7:0] = CLKOUT0_DIVIDE Integer part of clkout0 divide value For example, for 2.250, this value is 2 = 0x2 Bit[17:8] = CLKOUT0_FRAC Divide (3) Fractional part of clkout0 divide value For example, for 2.250, this value is 250 = 0xFA Note: You need not set any bit for specifying that the multiplier value is fractional. Just mention the fractional value in the register space. |
|
C_BASEADDR + 0x20C |
Clock Configuration Register 3 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKOUT0_PHASE (5) |
|
C_BASEADDR + 0x210 |
Clock Configuration Register 4 |
Default (2) : 0x0000C350 |
R/W |
Bit[31:0] = CLKOUT0_DUTY Duty cycle value = (Duty Cycle in %) * 1000 For example, for 50% duty cycle, value is 50000 = 0xC350 |
|
C_BASEADDR + 0x214 |
Clock Configuration Register 5 |
Default (2) : 0x0000000A |
R/W |
Bit[7:0] = CLKOUT1_DIVIDE (4) Eight bit clkout1 divide value |
|
C_BASEADDR + 0x218 |
Clock Configuration Register 6 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKOUT1_PHASE (5) Phase values entered are Signed Number for +/- phase |
|
C_BASEADDR + 0x21C |
Clock Configuration Register 7 |
Default (2) : 0x0000C350 |
R/W |
Bit[31:0] = CLKOUT1_DUTY (6) |
|
C_BASEADDR + 0x220 |
Clock Configuration Register 8 |
Default (2) : 0x0000000A |
R/W |
Bit[7:0] = CLKOUT2_DIVIDE (4) |
|
C_BASEADDR + 0x224 |
Clock Configuration Register 9 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKOUT2_PHASE (5) |
|
C_BASEADDR + 0x228 |
Clock Configuration Register 10 |
Default (2) : 0x0000C350 |
R/W |
Bit[31:0] = CLKOUT2_DUTY (6) |
|
C_BASEADDR + 0x22C |
Clock Configuration Register 11 |
Default (2) : 0x0000000A |
R/W |
Bit[7:0] = CLKOUT3_DIVIDE (4) |
|
C_BASEADDR + 0x230 |
Clock Configuration Register 12 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKOUT3_PHASE (5) |
|
C_BASEADDR + 0x234 |
Clock Configuration Register 13 |
Default (2) : 0x0000C350 |
R/W |
Bit[31:0] = CLKOUT3_DUTY (6) |
|
C_BASEADDR + 0x238 |
Clock Configuration Register 14 |
Default (2) : 0x0000000A |
R/W |
Bit[7:0] = CLKOUT4_DIVIDE (4) |
|
C_BASEADDR + 0x23C |
Clock Configuration Register 15 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKOUT4_PHASE (5) |
|
C_BASEADDR + 0x240 |
Clock Configuration Register 16 |
Default (2) : 0x0000C350 |
R/W |
Bit[31:0] = CLKOUT4_DUTY (6) |
|
C_BASEADDR + 0x244 |
Clock Configuration Register 17 |
Default (2) : 0x0000000A |
R/W |
Bit[7:0] = CLKOUT5_DIVIDE (4) |
|
C_BASEADDR + 0x248 |
Clock Configuration Register 18 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKOUT5_PHASE (5) |
|
C_BASEADDR + 0x24C |
Clock Configuration Register 19 |
Default (2) : 0x0000C350 |
R/W |
Bit[31:0] = CLKOUT5_DUTY (6) |
|
C_BASEADDR + 0x250 (3) |
Clock Configuration Register 20 |
Default (2) : 0x0000000A |
R/W |
Bit[7:0] = CLKOUT6_DIVIDE (4) |
|
C_BASEADDR + 0x254 (3) |
Clock Configuration Register 21 |
Default (2) : 0x00000000 |
R/W |
Bit[31:0] = CLKOUT6_PHASE (5) |
|
C_BASEADDR + 0x258 (3) |
Clock Configuration Register 22 |
Default (2) : 0x0000C350 |
R/W |
Bit[31:0] = CLKOUT6_DUTY (6) |
|
C_BASEADDR + 0x25C |
Clock Configuration Register 23 |
0x00000000 |
R/W |
Bit[0] = LOAD / SEN Loads Clock Configuration Register values to the internal register used for dynamic reconfiguration and initiates reconfiguration state machine. This bit should be asserted when the required settings are already written into Clock Configuration Registers. This bit retains to 0, when the dynamic reconfiguration is done and the clock is locked. Bit[1] = SADDR When written 0, default configuration done in the Clocking Wizard GUI is loaded for dynamic reconfiguration. When written 1, setting provided in the Clock Configuration Registers are used for dynamic reconfiguration. |
|
C_BASEADDR + 0x260 to C_BASEADDR + 0x7FC |
Undefined |
Undefined |
N/A (1) |
Do not read/write these registers. |
|
C_BASEADDR + 0x260 to C_BASEADDR + 0x2FC |
Undefined |
Undefined |
N/A |
|
|
Dynamic Reconfiguration Registers (when the Write DRP feature is enabled) |
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|
C_BASEADDR +0x300 |
Power Register |
FFFF |
R/W |
For more information, see MMCM and PLL Dynamic Reconfiguration (XAPP888) [Ref 6] . |
|
C_BASEADDR +0x304 |
CLKOUT0 Register 1 |
1145 |
R/W |
|
|
C_BASEADDR +0x308 |
CLKOUT0 Register 2 |
0000 |
R/W |
|
|
C_BASEADDR +0x30C |
CLKOUT1 Register 1 |
1145 |
R/W |
|
|
C_BASEADDR +0x310 |
CLKOUT1 Register 2 |
00C0 |
R/W |
|
|
C_BASEADDR +0x314 |
CLKOUT2 Register 1 (Not available for PLLE3) |
1145 |
R/W |
|
|
C_BASEADDR +0x318 |
CLKOUT2 Register 2 (Not available for PLLE3) |
00C0 |
R/W |
For more information, see MMCM and PLL Dynamic Reconfiguration (XAPP888) [Ref 6] . |
|
C_BASEADDR +0x31C |
CLKOUT3 Register 1 (Not available for PLLE3) |
1145 |
R/W |
|
|
C_BASEADDR +0x320 |
CLKOUT3 Register 2 (Not available for PLLE3) |
00C0 |
R/W |
|
|
C_BASEADDR +0x324 |
CLKOUT4 Register 1 (Not available for PLLE3) |
1145 |
R/W |
|
|
C_BASEADDR +0x328 |
CLKOUT4 Register 2 (Not available for PLLE3) |
00C0 |
R/W |
|
|
C_BASEADDR +0x32C |
CLKOUT5 Register 1 |
1145 |
R/W |
|
|
C_BASEADDR +0x330 |
CLKOUT5 Register 2 |
00C0 |
R/W |
|
|
C_BASEADDR +0x334 |
CLKOUT6 Register 1 (Not available for PLLE2 or PLLE3) |
1145 |
R/W |
|
|
C_BASEADDR +0x338 |
CLKOUT6 Register 2 (Not available for PLLE2 or PLLE3) |
00C0 |
R/W |
|
|
C_BASEADDR +0x33C |
DIVCLK Register |
1041 |
R/W |
|
|
C_BASEADDR +0x340 |
CLKFBOUT Register 1 |
1145 |
R/W |
|
|
C_BASEADDR +0x344 |
CLKFBOUT Register 2 |
0000 |
R/W |
|
|
C_BASEADDR +0x348 |
Lock Register 1 |
03e8 |
R/W |
|
|
C_BASEADDR +0x34C |
Lock Register 2 |
7001 |
R/W |
|
|
C_BASEADDR +0x350 |
Lock Register 3 |
73E9 |
R/W |
|
|
C_BASEADDR +0x354 |
Filter Register 1 |
800 |
R/W |
For more information, see MMCM and PLL Dynamic Reconfiguration (XAPP888) [Ref 6] . |
|
C_BASEADDR +0x358 |
Filter Register 2 |
9190 |
R/W |
|
|
C_BASEADDR +0x35C |
Clock Configuration Register 24s |
0000 |
R/W |
Bit[0] = LOAD / SEN Loads Clock Configuration Register values to the internal register used for dynamic reconfiguration and initiates reconfiguration state machine. This bit should be asserted when the required settings are already written into Clock Configuration Registers. This bit retains to 0, when the dynamic reconfiguration is done and the clock is locked. Bit[1] = SADDR When written 0, default configuration done in the Clocking Wizard GUI is loaded for dynamic reconfiguration. When written 1, setting provided in the Clock Configuration Registers are used for dynamic reconfiguration. |
|
C_BASEADDR + 0x360 to C_BASEADDR + 0x7FC |
Undefined |
Undefined |
N/A |
|
|
Notes: 1. Reading of this register returns an undefined value. 2. Initialized with configuration settings done by the clocking algorithm. 3. Valid only for MMCM(E2/E4) primitive. 5. Phase value = (Phase Requested) * 1000. For example, for a 45.5 degree phase, the required value is 45500 = 0xB1BC. 6. Phase values entered are signed numbers in the range +360000 to -360000. 7. Duty cycle value = (duty cycle in %) * 1000. For example, for a 50% duty cycle, the value is 50000 = 0xC350. 8. To enable the interrupt, the user must write to the interrupt enable register with all 1's. Clock overrun and clock underrun are bits gated by interrupt enable bits. Interrupts corresponding to the enabled bits in the interrupt enable register are updated in this register. |
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Note: You need to write all the register sets with the required values, even if you want the change only in one particular register.