Resets - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

The Clocking Wizard has an active-High asynchronous reset signal for the clocking primitive.

The core must be held in reset during clock switch over.

When the input clock or feedback clock is lost, the clkinstopped or clkfbstopped status signal is asserted. After the clock returns, the clkinstopped signal is deasserted and a reset must be applied.