The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
04/20/2022 |
6.0 |
• Added the Artix UltraSale and UltraScale+ Data sheets support in Maximum Frequencies . • Updated the content in the MMCM Counter Cascading section. • Updated the note in the Example for Dynamic Reconfiguration through AXI4-Lite section. |
|
08/06/2021 |
6.0 |
• Updated output clock ports in Table: Clocking Wizard I/O . • Added note to Clock Out of Range . • Added Optimal Clocking Structure . • Added bullet to Selecting Clocking Features . • Updated note about fractional divide values to Configuring Output Clocks . • Added note to Debug for Dynamic Reconfiguration . |
|
03/18/2021 |
6.0 |
• Added note to Table: Clocking Wizard I/O and Table: Clock Configuration Registers . • Updated the number of clock cycles in the Clock Stop section. • Added content to the Dynamic Reconfiguration through AXI4-Lite section. • Added a description to the command line in the Required Constraints section. • Updated settings in step 3 of Safe Clock Startup Timing Failures for UltraScale and UltraScale+ Devices . |
|
02/05/2020 |
6.0 |
• Updated IP Facts . • Updated binary in note in Example for Dynamic Reconfiguration through AXI4-Lite . |
|
02/25/2019 |
6.0 |
• Added note explaining that the Port Renaming tab has been removed in Selecting Clocking Features . • Added note about OVERRIDE_PRIMITIVE parameter in Overriding Calculated Parameters . • Added note about Dynamic Reconfiguration in the DRP interface in Example for Dynamic Reconfiguration Using Write to DRP . |
|
04/04/2018 |
6.0 |
• Updated for core version • Updated phase alignment feature in Selecting Clocking Features • Updated Configuring Output Clocks section in Design Flow Steps |
|
10/04/2017 |
5.4 |
• Added Wiki link of clock framework for Linux Operating System • Updated for minor corrections |
|
04/05/2017 |
5.4 |
• Updated for core version • Updated IP GUI screens in Design Flow Steps |
|
10/05/2016 |
5.3 |
• Added a special feature AUTO in primitive selection. • Added Auto Inference section in Design Flow Steps . |
|
06/08/2016 |
5.3 |
• Added a sub section heading for the register space. • Segregated the Clocking Wizard I/O table contents. |
|
04/06/2016 |
5.3 |
• Updated for core version • Added support for clock monitoring. • Added the write DRP feature for non-utilization of DSP resources in dynamic reconfiguration. • Consolidated the redundant bits of clock configuration register 23. |
|
11/18/2015 |
5.2 |
• Added support for UltraScale+ architecture-based devices. |
|
09/30/2015 |
5.2 |
• Updated for core version and IP GUI screens • Removed the VHDL support for example design and simulation files • Removed the unsupported Port-Renaming Tab from GUI in IP Integrator |
|
04/01/2015 |
5.1 |
• Added the Minimum Input frequencies for MMCM and PLL for Virtex-7 devices. • Added an example describing the reference steps when using the AXI Interface for using the dynamic reconfiguration interface. |
|
10/01/2014 |
5.1 |
Added UltraScale architecture support and User Parameters mapping table. |
|
10/01/2014 |
5.1 |
Added UltraScale architecture support and User Parameters mapping table. |
|
04/02/2014 |
5.1 |
Updated Configuring Output Clock section. Added Resource utilization for AXI4-Lite interface using Kintex-7 device. |
|
12/18/2013 |
5.1 |
Added UltraScale Architecture support. |
|
10/02/2013 |
5.1 |
Updated for to synch doc version with core version. Added Migration information. |
|
03/20/2013 |
1.3 |
Updated for core version, added XCI parameters and Safe Clock Startup diagrams and waveforms. |
|
12/18/2012 |
1.2 |
Updated for core version, active-Low RESET support, and Vivado GUI screens. |
|
10/16/2012 |
1.1 |
Updated for core version and Vivado GUI screens. |
|
07/25/2012 |
1.0 |
Initial release of Product Guide, replacing DS709 and UG521. |