Safe Clock Startup Timing Failures for UltraScale and UltraScale+ Devices - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

For UltraScale or UltraScale+ devices, when the Safe Clock Startup feature is enabled and the clocks are operating at more than 300 MHz frequency, the design might not meet timing. Use the following steps to meet the timing during implementation:

1. Add an additional BUFGCE cascaded in the failing clock path along with the existing BUFGCE in safe clock startup path. This Figure shows the failing path for the clk_out1 . Insert New BUFGCE between MMCM and the BUFGCE2 as shown below.

Figure C-1: Safe Clock Startup Failing Path

X-Ref Target - Figure C-1


2. Apply the DONT_TOUCH constraint to the newly added BUFGCE . The DONT_TOUCH is necessary to prevent opt_design from removing the newly inserted cascaded BUFGCE .

(* dont_touch = "true" *) wire <<signal_name>>;

3. Set CLOCK_DELAY_GROUP and USER_CLOCK_ROOT between the newly added cascaded BUFGCE and the BUFGCE for the safe startup circuit to ensure that they are balanced.

set_property CLOCK_DELAY_GROUP group_bufgce [get_nets <<BUFG_CE1_net>>]

set_property CLOCK_DELAY_GROUP group_bufgce [get_nets <<new_BUFGCE_net>>]

set_property CLOCK_REGION <<CLOCK_REGION_XX_YY>> [get_cells <<BUFG_CE1>>]

set_property CLOCK_REGION <<CLOCK_REGION_XX_YY>> [get_cells <<BUFG_CE2>>]

set_property CLOCK_REGION <<CLOCK_REGION_XX_YY>> [get_cells <<new_BUFGCE>>]

CLOCK_REGION is needed to place the cascaded BUFGCE buffers in the same clock region to reduce the delay between them.

Note: <CLOCK_REGION_XX_YY> is the CLOCK_REGION where the MMCM resides and should be in the same region as the MMCM clock input pin.