Simulation Waveforms for the Safe Clock Startup Feature - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)
Document ID
PG065
Release Date
2022-04-20
Version
6.0 English

Simulation when Safe Clock Startup is true is illustrated in This Figure .

Figure 4-20: Simulation When Safe Clock Startup is True

X-Ref Target - Figure 4-20

pg065_fig4-13.jpg

This Figure illustrates simulation when Safe Clock Startup is true and Use Clock Sequencing is true, with the required sequence number in the table.

Figure 4-21: Simulation when Safe Clock Startup is True and Use Clock Sequencing is True

X-Ref Target - Figure 4-21

pg065-sim-safe-clk-true.jpg

IMPORTANT: For cores targeting 7 series or Zynq ® -7000 devices, UNIFAST libraries are not supported. Xilinx IP is tested and qualified with UNISIM libraries only.