This chapter contains information about the provided test bench in the Vivado® Design Suite environment. The following file describes the demonstration test bench:
• Verilog
<project_name>/<project_name>.srcs/sources_1/ip/<component_name>/simulation/<component_name>_tb.v
The demonstration test bench is a simple Verilog program designed to exercise the example design and the core. It performs frequency calculations as well as checks of all the output clocks. It reports all the output clock frequencies, and if any of the output clocks is not generating the required frequency, it reports an error.
Note: Test bench files are delivered only in Verilog.