Visibility of Clock Ports - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

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6.0 English

The new Wizard provides a clocking network that matches your requirements rather than making clock ports visible. As a result, your clock names do not match the exact names for the primitive. For example, while the first clock available for the Virtex-6 FPGA MMCM is CLKOUT0 , the highest-priority clock available to you is actually named CLK_OUT1 .

IMPORTANT: This change in numbering is especially important to consider if parameter overriding is desired.