The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design. The debug feature also allows the you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx.
The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:
• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)
See Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 3] .