This Figure shows a normal operation with link up in the AXI Chip2Chip core for SelectIO™ PHY interface.
This Figure shows a calibration failure in the Slave device in the AXI Chip2Chip core for SelectIO PHY interface.
This Figure shows a calibration failure in the Master device in the AXI Chip2Chip core for SelectIO ™ PHY interface.
Note: Link error recovery is possible only after going through reset cycle.
IMPORTANT: A Master or Slave device can fail in self-calibration if there is a physical or transient fault on the link or if there is physical connection error.
The AXI Chip2Chip core implements Link Detect FSM for device detection and calibration functions for the SelectIO PHY interface. The calibration process is initiated when either the Master or Slave AXI Chip2Chip is brought out of reset. During the calibration process, a fixed set of patterns are exchanged between the Master and Slave devices. The receiving device responds with an appropriate pattern if received patterns do not match the expected fixed patterns. Deskew operations align the data until an optimized sampling point is determined. After the patterns are determined to match for the greatest number of the sampling points, the receiving device responds with an ACK. This operation is performed at nibble level for 32 sampling points. The best sampling point is determined for each nibble in the data. Link status is asserted after both Master and Slave devices respond with an ACK. The Link Failure ( axi_c2c_multi_bit_error_out ) signal is asserted when a multi-bit error is determined during deskew operations and indicates the failure of those operations. In this case, either the interface rate can be reduced or I/O Type can be appropriately selected to achieve the required interface rate.
When the Link Status signal is asserted, the AXI Chip2Chip core transparently bridges transactions in compliance with AXI protocol specifications. It is not recommended to reset or disconnect either the Master or Slave AXI Chip2Chip core during normal operation or when the Link Status signal is asserted. When the Slave device is reset or if the cable is disconnected during normal operations, the Link Status signal is deasserted and a link error interrupt is asserted in the Master device. After being asserted, a link error interrupt can be cleared only with a reset. The AXI Chip2Chip core operations are re-initiated when the Master and Slave AXI Chip2Chip devices are brought out of reset, when using an Aurora PHY interface.
This Figure shows a normal operation with link up in the AXI CHip2Chip core, for the Aurora Mode.
This Figure shows a configuration error in the AXI Chip2Chip core, for the Master Aurora Mode.
Note: A Master device in Aurora mode can assert the configuration error status signal. An asserted configuration error status signal indicates the Link Detect FSM failed due to a configuration mismatch of Master and Slave AXI Chip2Chip cores. Recovery from a configuration error is only possible after going through a reset cycle.