• Supports AXI4 Memory Map interface data width of 32-bit, 64-bit and 128-bit.
• Supports optional AXI4-Lite data width of 32-bit
• Two interface choices:
° Single Ended or Differential SelectIO™ interface
° Aurora interface that provides AXI4-Stream interface to seamlessly integrate into the Aurora IP core
• Independent Master or Slave mode selection for AXI4 and AXI4-Lite interfaces
• Supports Common Clock or Independent Clock operations
• Supports multiple Width Conversion options for reduced I/O utilization
• Supports Link Detect FSM with deskew operation for the SelectIO ™ interface
• Supports Link Detect FSM and implements Hamming SECDED error correction code (ECC) for Aurora interfaces
• Allows all five AXI4 channels to operate independently
• Supports an additional high-priority cut through channel for communicating interrupts
• Supports completion of the pending AXI transactions in case the link fails between chip2chip master and chip2chip slave
• Provides a dedicated high-priority internal channel for link status monitoring and reporting.
LogiCORE ™ IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
Versal®, UltraScale+™ Families, UltraScale™ Architecture, Zynq®-7000, Xilinx 7 series |
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Supported User Interfaces |
AXI4, AXI4-Lite |
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Resources |
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Provided with Core |
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Design Files |
Verilog |
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Example Design |
Verilog |
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Test Bench |
Verilog |
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Constraints File |
XDC |
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Simulation Model |
Not Provided |
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Supported
|
N/A |
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Tested Design Flows (2) |
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Design Entry |
Vivado ® Design Suite |
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Simulation |
For support simulators, see th
e
|
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54806 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete list of supported devices, see the Vivado® IP catalog. 2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide . |