A data phase timeout is implemented in the AXI to APB Bridge core, when c_dphase_timeout is not equal to 0. When a request is issued from the AXI interface, the AXI to APB Bridge core translates this request into a corresponding APB transfer. If there is no response to the request by the APB slave (m_apb_pready is not asserted), the core waits for the number of clock cycles defined in the timeout generic and then responds to AXI with SLVERR response (and drives zeroes on s_axi_rdata during the read transfer). For more information about timeouts, see Basic.