The 32-bit AXI4-Lite interface on the AXI to APB Bridge core is based on the AMBA® AXI and ACE Protocol Specification v2.0 [Ref 1]. The core functions as a 32-bit slave on this interface.
The 32-bit APB interface of the core is based on the AP3 interface as described in the AMBA APB Protocol Specification v2.0 [Ref 1]. The core supports the optional APB4 interface as well. The core functions as a 32-bit master on the APB3/APB4 interface.
The AXI to APB Bridge core supports a 1:1 (AXI:APB) synchronous clock ratio as well as data phase timeout.