Overview - 3.0 English

AXI to APB Bridge Product Guide (PG073)

Document ID
PG073
Release Date
2022-05-17
Version
3.0 English

The top module instantiates all components of the core and example design that are needed to implement the design in hardware, as shown in This Figure. This includes clock generator (MMCME2) and example design module with logic for AXI transaction generator and APB transaction checker.

Figure 5-1:      Block Diagram of Example Design

X-Ref Target - Figure 5-1

pg073_block_diag_example_x13760.jpg

This example design demonstrates transactions on AXI interfaces of the DUT.

Clock generator: MMCME2 is used to generate the clock for the example design. It generates 100 MHz clock for s_axi_aclk of the DUT. The DUT is under reset until MMCME2 is locked.

AXI transaction generation: Handles write and read transactions on the AXI-Lite interface of the bridge.

Capture APB transaction: Serves as the APB slave to the bridge and handles write and read transactions from the AXI interface of the bridge.