Vivado Design Suite Debug Feature - 3.0 English

AXI to APB Bridge Product Guide (PG073)

Document ID
PG073
Release Date
2022-05-17
Version
3.0 English

The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design. The debug feature also allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx devices.

The Vivado logic analyzer is used with the logic debug LogiCORE IP cores, including:

ILA 2.0 (and later versions)

VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 9].

The interface is not being held in reset, and s_axi_areset is an active-Low reset.

The interface is enabled, and s_axi_aclken is active-High (if used).

The main core clocks are toggling and that the enables are also asserted.

If the simulation has been run, verify in simulation or a Vivado lab tools capture that the waveform is correct for accessing the AXI4-Lite interface.