Aurora 64B/66B Simplex Normal Operation Reset Sequence - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
Release Date
12.0 English

For simplex configurations, because the TX and RX can be powered on independently, data transmission must begin only after rx_channel_up is seen (that is, after a minimum of 45 ms of tx_channel_up ), to avoid loss of data., Before asserting pma_init , the reset_pb must be asserted for a minimum time equal to 128* user_clk time period to ensure that the portion of the core in programmable logic goes to a known reset state before the user_clk is held Low during pma_init assertion. The assertion time of pma_init must be a minimum of six INIT_CLK cycle time period to satisfy the requirements of the core de-bouncing circuit.

Figure 3-5: Aurora 64B/66B Simplex Normal Operation Reset Sequence

X-Ref Target - Figure 3-5