CRC Interface - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID

PG074

Release Date

2023-05-17

Version

12.0 English

CRC is an optional interface. The crc_valid and crc_pass_fail_n signals ( Table: CRC Interface Ports ) indicate the result of a received frame transmitted with CRC. See Using CRC for more information.

Table 2-14: CRC Interface Ports
Name	Direction	Clock Domain	Description
CORE_STATUS
crc_valid	Output	user_clk	Samples the crc_pass_fail_n signal.
crc_pass_fail_n	Output	user_clk	The crc_pass_fail_n signal is asserted as High when the received CRC matches the transmitted CRC. This signal is not asserted if the received CRC is not equal to the transmitted CRC. The crc_pass_fail_n signal should always be sampled with the crc_valid signal.

This Figure illustrates checking CRC at the core level. The figure shows 6 n bytes of received data of a frame. At the end of the frame, the core asserts m_axi_rx_tlast and crc_valid . In the same clock cycle, the transmitted and computed CRCs are compared. If the values match, the crc_pass_fail_ n signal is asserted.

Figure 2-38: A 6 n Data Beats Frame with CRC