Clock Compensation Logic - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

The Aurora 64B/66B core includes a clock compensation module that is used to generate periodic clock compensation sequences in accordance with the Aurora 64B/66B Protocol Specification (SP011) [Ref 9] .

The clock compensation feature allows up to ±100 ppm difference in the reference clock frequencies used on each side of an Aurora 64B/66B channel.

To perform Aurora 64B/66B-compliant clock compensation, the clock compensation sequence is sent every 4,992 user_clk cycles. The CC sequence consists of a maximum of 8 CC characters. The signal s_axi_tx_tready is deasserted on the TX user interface while the channel is being used to transmit clock compensation sequences.

Figure 3-18: Streaming Data with Clock Compensation Inserted

X-Ref Target - Figure 3-18

pg074_streaming_data_cc_inserted_X14637.jpg
Figure 3-19: Data Reception Interrupted by Clock Compensation

X-Ref Target - Figure 3-19

pg074_data_reception_cc_interrupt_x14622.jpg

The most common use of this feature is scheduling clock compensation events to occur outside of frames, or at specific times during a stream to avoid interrupting data flow.

IMPORTANT: The parameter CC_FREQ_FACTOR determines the frequency of the CC sequence. It is fixed at 24. Any attempt to increase or decrease this parameter should be done with careful analysis and testing.

Following are the clock compensation logic customizing guidelines:

Ensure that the duration and period selected are sufficient to correct for the maximum difference between the frequencies of the clocks used.

Do not perform multiple clock compensation sequences within eight cycles of one another.