Aurora 64B/66B example design clock constraints can be grouped into the following three categories:
• GT reference clock constraint
The Aurora 64B/66B core uses one minimum reference clock and two maximum reference clocks for the design. The number of GT reference clocks is derived based on transceiver selection (that is, lane assignment in the second page of the Vivado IDE). The GT REFCLK value selected in the first page of the Vivado IDE is used to constrain the GT reference clock.
Note: The GT reference clock location constraint should be added to the <user_component_name>_example.xdc file.
• CORECLK clock constraint
CORECLKs are the clock signals on which the core functions. CORECLKs such as USER_CLK and SYNC_CLK are derived from the TXOUTCLK signal from the master lane. The master lane is the selected lane itself if it is a single lane configuration. In case of multi-lane configuration, it is chosen from the middle lane amongst the number of lanes configured. For example, a seven lane design would have the middle lane as the third lane ( TXOUTCLK) . The Aurora 64B/66B core calculates the USER_CLK/SYNC_CLK frequency based on the line rate and transceiver interface width. The create_clock XDC command is used to constrain all CORECLKs.
• INIT CLK constraint
The Aurora 64B/66B example design uses a debounce circuit to sample PMA_INIT asynchronously clocked by the init_clk clock. The create_clock XDC command is used to constrain the init_clk clock. The init_clk frequency value in Vivado IDE is restricted to six decimal places.
RECOMMENDED: It is recommended to have the system clock frequency lower than the transceiver reference clock frequency and in the range of 50 to 200 MHz for 7 series and Zynq devices. For UltraScale devices, the recommended range is 6.25 MHz to line_rate/64 or 200 MHz whichever is less.See UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 5] and UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 6] for more information on valid use models for the free running system clock ( init_clk ).