Clock Interface - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

Table: Aurora 64B/66B Core Clock Ports describes the core clock ports. In GTX, GTH or GTY transceiver designs, the reference clock can be taken from the GTXQ/GTHQ/GTYQ signal, which is a differential input clock for each GTX, GTH or GTY transceiver. The reference clock for GTX/GTH/GTY transceivers is provided through the clkin port. For more details on the clock interface, see Clocking .

IMPORTANT: This interface is most critical for correct Aurora 64B/66B core operation. The clock interface has ports for the reference clocks that drive the GTX,GTH or GTY transceivers and ports for the parallel clocks that the core shares with application logic.

Table 2-7: Aurora 64B/66B Core Clock Ports

Name

Direction

Clock Domain

Description

init_clk/init_clk_p/init_clk_n

Input

-

The init_clk signal is used to register and debounce the pma_init signal. The preferred init_clk range is 50 to 200 MHz. The default init_clk frequency set by the core is 50 MHz for 7 series designs and line_rate/64 for UltraScale device designs. init_clk frequency is a user-configurable parameter. With the Include Shared Logic in core option, the init_clk signal is differential. The Single Ended INIT CLK option provides single-ended init_clk input.


For Versal ACAP, UltraScale, and UltraScale+ device designs:
Refer to the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331) [Ref 31] , UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 5] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 6] , when applicable. for more details on the range of allowable frequency as specified in GUI customization. init_clk is also connected to the DRPCLK port of the GTHE3/GTYE3/GTHE4/GTYE4 CHANNEL interface.

init_clk_out (2)

Output

init_clk

Init clock output. This port is not available for Single Ended INIT CLK option because UltraScale and UltraScale+ devices do not have differential init_clk input.

mmcm_not_locked

Input

user_clk

If mixed-mode clock manager (MMCM) is used to generate clocks for the Aurora 64B/66B core, the mmcm_not_locked signal should be connected to the inverse of the serial transceiver phase-locked loop (PLL) locked signal. The clock modules provided with the core use the PLL for clock division. The mmcm_not_locked signal from the clock module should be connected to the core mmcm_not_locked signal. The mmcm_not_locked signal is available when shared logic is included in the example design.

For UltraScale and UltraScale+ devices:
mmcm_not_locked is connected to gtwiz_
userclk_tx_active_out driven from the <user_component_name>_ultrascale_
tx_userclk module. The signal is driven based on the clocking helper core status and signifies that the helper core is out of reset. Active High signal. The mmcm_not_locked_out signal is available when shared logic is included in the core. The mmcm_not_locked is part of the CORE_CONTROL interface. mmcm_not_locked_out is part of the CORE_STATUS interface.

mmcm_not_locked_out

Output

user_clk

user_clk

Input

Parallel clock shared by the core and the user

application. The user_clk signal is a BUFG

output deriving its input from tx_out_clk. The

clock generators are available in the <component

name>_clock_module file. user_clk serves as

the txusrclk2 input to the transceiver. See the

related transceiver user guide/data sheet for

rate-related information. user_clk is available

when shared logic is included in the example

design. user_clk_out is the user clock output which is available when shared logic is included in the core.

user_clk_out (2)

Output

user_clk

tx_out_clk

Output

tx_out_clk

Generated from the GTX, GTH or GTY transceiver

reference clock based on the transceiver PLL

frequency setting. Should be buffered and used

to generate the user clock for the logic connected

to the core.

bufg_gt_clr_out (6)

Output

init_clk

This signal needs to be connected to the clock locked input of the clock module when using shared logic in the example design.

sync_clk

Input

-

Parallel clock used by the serial transceiver

internal synchronization logic. Provided as the

txusrclk signal to the transceiver interface. The

sync_clk is twice the rate of user_clk. See the

related transceiver user guide/data sheet for

rate-related information. sync_clk is available

when shared logic is included in the example

design. sync_clk_out is the sync clock output. This port is not available in RX-only_Simplex mode.

sync_clk_out (2)

Output

sync_clk

gt_refclk1_p/gt_refclk1_n

gt_refclk2_p/gt_refclk2_n

gt_refclk3_p/gt_refclk3_n (8)

gt_refclk4_p/gt_refclk4_n (8)

gt_refclk5_p/gt_refclk5_n (8)

refclk1_in

refclk2_in

refclk3_in (8)

refclk4_in (8)

refclk5_in (8)

Input

-

gt_refclk ( clkp / clkn ) is a dedicated external clock generated from an oscillator and fed

through a dedicated IBUFDS.

gt_refclk1_p/gt_refclk1_n = Differential Transceiver Reference Clock 1 (2) .

gt_refclk2_p/gt_refclk2_n = Differential Transceiver Reference Clock 2 (3)

gt_refclk3_p/gt_refclk3_n = Differential Transceiver Reference Clock 2 (8)

gt_refclk4_p/gt_refclk4_n = Differential Transceiver Reference Clock 2 (8)

gt_refclk5_p/gt_refclk5_n = Differential Transceiver Reference Clock 2 (8)

refclk1_in = Single Ended Transceiver Reference Clock 1 (4) .

refclk2_in = Single Ended Transceiver Reference Clock 2 (5) .

gt_refclk1_out = Single Ended Transceiver Reference Clock 1 (2) .

gt_refclk2_out = Single Ended Transceiver Reference Clock 1 (3) . Not available for the Single Ended GT REFCLK option.

gt_refclk1_out

gt_refclk2_out

gt_refclk3_out (8)

gt_refclk4_out (8)

gt_refclk5_out (8)

Output

-

gt_rxusrclk_out (7)

Output

rxoutclk

Receiver recovered clock from the master GT channel of the Aurora64b66b core. This output clock port is enabled only when Additional Transceiver Control and Status Ports option is enabled during the Aurora 64b66b core customization.

gt_qpllclk_quad< quad_no >_in, gt_qpllrefclk_quad< quad_no >_in (1)

Input

-

Clock inputs generated by GTXE2_COMMON/GTHE2_COMMON/GTHE3_
COMMON/GTYE3_COMMON, GTHE4_COMMON, GTYE4_COMMON.

gt_qpllclk_quad< quad_no >_out, gt_qpllrefclk_quad< quad_no >_out (1)

Output

-

Clock outputs generated by GTXE2_COMMON/GTHE2_COMMON/
GTHE3_COMMON/GTHE4_COMMON/GTYE3_COMMON/GTYE4_COMMON. If the line rate is < 6.6 Gb/s in the GTX transceivers and < 8.0 Gb/s in 7 series. In UltraScale and UltraScale+ FPGA GTH and GTY transceivers, the gt_qpllclk_quad< quad_no >_out signal is tied High.

Notes:

1. In 7 series, quad_no varies from 1 to the number of active transceiver quads –1. In UltraScale and UltraScale+ FPGAs, varies from 1 to the number of active transceiver quads.

2. Enabled when Include Shared Logic in Core is selected.

3. Enabled when Include Shared Logic in Core is selected and more than one reference clock is required.

4. Enabled when Include Shared Logic in Example Design is selected or enabled when Include Shared Logic in Core is selected and if the single-ended option is selected.

5. Enabled when Include Shared Logic in Example Design is selected and more than one reference clock is required or enabled when Include Shared Logic in Core is selected and more than one reference clock is required and if the single-ended option is selected.

6. Enabled when Include Shared Logic in Example Design is selected for UltraScale and UltraScale+ designs.

7. gt_rxusrclk_out is the output from BUFGCE which has the input source clock as rxoutclk from the GT in 7 series devices. In UltraScale and UltraScale+, It is the output from GT RX clocking helper module.

8. These clocks are enabled depending on the number of active transceiver quads chosen by designer in GTY based designs when the line rate is > 16.375 Gb/s.

9. For Versal ACAP, GT is always outside of Aurora IP. GT location constraints are not delivered by Aurora IP.