This product guide describes the function and operation of the AMD LogiCORE™ IP Aurora 64B/66B core and provides information about designing, customizing, and implementing the core.
Aurora 64B/66B is a lightweight, serial communications protocol for multi-gigabit links (as shown in the following figure). It is used to transfer data between devices using one or many GTX, GTH, or GTY transceivers. Connections can be full-duplex (data in both directions) or simplex (data in either one of the directions).
The Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX, GTH, or GTY transceivers in applicable AMD Versal™ , AMD UltraScale+™ , AMD UltraScale™ , AMD Zynq™ 7000, AMD Virtex™ 7, and AMD Kintex™ 7 devices. A single instance of Aurora 64B/66B core can use up to 16 valid consecutive lanes on GTX, GTH, or GTY transceivers running at any supported line rate to provide a low-cost, general-purpose, data channel with throughput from 500 Mbps to over 400 Gbps.
Aurora 64B/66B cores are verified for protocol compliance using an array of automated simulation tests.
Aurora 64B/66B cores automatically initialize a channel when they are connected to an Aurora 64B/66B channel partner. After initialization, applications can pass data across the channel as frames or streams of data. Aurora 64B/66B frames can be of any size. A high-priority request is capable of interrupting these frames at any time. Gaps between valid data bytes are automatically filled with idles to maintain a lock and prevent excessive electromagnetic interference. Flow control is optional in Aurora 64B/66B and can be used to throttle the link partner’s transmit data rate, or to send brief high-priority messages through the channel.
Streams are implemented in Aurora 64B/66B as a single unending frame. Whenever data is not being transmitted, idles are transmitted to keep the link alive. Excessive bit errors, disconnections, or equipment failures cause the core to reset and attempt to initialize a new channel. The Aurora 64B/66B core can support a maximum of two symbols skew in the receipt of a multi-lane channel. The Aurora 64B/66B protocol uses 64B/66B encoding. The 64B/66B encoding offers theoretically improved performance because of its very low (3%) transmission overhead, compared to 25% overhead for 8B/10B encoding.
- Although the Aurora 64B/66B core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, prior experience in building high-performance, pipe lined FPGA designs using the AMD implementation tools and Xilinx Design Constraints (XDC) user constraints files is recommended.
- Consult the PCB design requirements information in UltraScale Architecture GTH Transceivers User Guide (UG576), UltraScale Architecture GTY Transceivers User Guide (UG578), 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476), Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002), and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017). Contact your local AMD representative for a closer review and estimation for your specific requirements.