Customizing and Generating the Core - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
Release Date
12.0 English

This section includes information about using Xilinx tools to customize and generate the core in the Vivado Design Suite.

When customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 11] for detailed information. The IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl Console.

Use the following steps to customize the IP for use in your design by specifying values for the various parameters associated with the IP core:

1. Select the IP from the Vivado IP catalog ( IP Catalog -> Aurora 64B66B ).

2. Double-click the selected IP or select Customize IP from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 12] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 13] .

The Aurora 64B/66B core can be customized to suit a wide variety of requirements using the IP catalog. This chapter details the customization parameters and how these parameters are specified within the Vivado Integrated Design Environment (IDE).

This Figure through This Figure show the features described in the corresponding sections. The left side displays a representative block diagram of the Aurora 64B/66B core as currently configured. The right side consists of user-configurable parameters.

This Figure shows the Core Options tab of the Customize IP interface with the default options for Zynq®-7000 and 7 series devices.

This Figure shows the Core Options tab for UltraScale™ and UltraScale+™ devices. Details on the customizing options are provided in the following subsections, starting with Component Name .

Note: Figures in this chapter are illustrations of the Vivado IDE. This layout depicted here might vary from the current version.