Detailed Example Design - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

Each Aurora 64B/66B core includes an example design ( <user_component_name>_exdes ) that uses the core in a simple data transfer system. For more details about the example_design directory, see Output Generation .

The example design based on the selected configurations consists of the following:

Frame generator ( FRAME_GEN ) connected to the TX interface

Frame checked ( FRAME_CHECK ) connected to the RX user interface

VIO/ILA instance for debug and testing

Hardware-based reset fsm to perform repeat reset and channel integrity testing (only for duplex mode)

The following figure shows a block diagram of the example design for a full-duplex core. Table: Example Design I/O Ports describes the ports of the example design.

Figure 5-1: Example Design

X-Ref Target - Figure 5-1

pg074_example-design-viv_x13038.jpg

The example design uses all the interfaces of the core. There are separate AXI4-Stream interfaces for optional flow control. Simplex cores without a TX or RX interface have no FRAME_GEN or FRAME_CHECK block, respectively.