Device Migration - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

If migrating from a 7 series device with GTX or GTH transceivers to an UltraScale™ device with GTH transceivers, the prefixes of the optional transceiver debug ports for single-lane cores are changed from “ gt0 ”, “ gt1 ”   to “ gt ”, and the suffix “ _in ” and “ _out ” are dropped. For multi-lane cores, the prefixes of the optional transceiver debug ports gt(n) are aggregated into a single port. For example: gt0_gtrxreset and gt1_gtrxreset now become gt_gtrxreset [1:0] . This is true for all ports, with the exception of the DRP buses which follow the convention of gt(n)_drpxyz .

IMPORTANT: It is important that designs are updated to use the new transceiver debug port names. For more information about migration to UltraScale devices, see the UltraScale Architecture Migration Methodology Guide (UG1026) [Ref 16] .

Perform any one of the following steps when migrating to Versal ACAP:

Instantiate Aurora IP in the IP integrator. For more information, see Xilinx IP - GT Quad Integration .

Generate Aurora IP from Vivado IP catalog, open example design. Versal ACAP Aurora IP example design has an IPI based reference design as shown in This Figure . Refer the example design wrapper file <IP_inst_name>_exdes_bd_wrapper as shown in This Figure . This wrapper file has the necessary connections between Aurora and gt_quadbase IP. For more information, see Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331) [Ref 31] .

Figure B-1: Aurora Example Design

X-Ref Target - Figure B-1

Aurora_example_design.png
Figure B-2: Aurora Example Design BD Wrapper

X-Ref Target - Figure B-2

Aurora_Example_Design_BD_Wrapper.png