Example A: Data Reception with Pause - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

This Figure shows an example of 3 n bytes of received data interrupted by a pause. Data is presented on the m_axi_rx_tdata bus. When the first n bytes are placed on the bus, the m_axi_rx_tvalid output is asserted to indicate that data is ready for the user application.

Figure 2-11: Data Reception with Pause

X-Ref Target - Figure 2-11

pg074_data-reception-with-pause_x13034.jpg

After the pause, the core asserts m_axi_rx_tvalid and continues to assemble the remaining data on the m_axi_rx_tdata bus. At the end of the frame, the core asserts m_axi_rx_tlast . The core also computes the value of the m_axi_rx_tkeep bus and presents it to the user application based on the total number of valid bytes in the final word of the frame.