This Figure shows a typical streaming data transfer beginning with neither of the ready signals asserted to indicate that both the user logic and the core are not ready to transfer data. During the next clock cycle, the core indicates that it is ready to transfer data by asserting s_axi_tx_tready . One cycle later, the user logic asserts the s_axi_tx_tvalid signal and places data on the s_axi_tx_tdata bus indicating that it is ready to transfer data. Because both signals are now asserted, Databeat 0 as shown in This Figure is transferred from the user logic to the core. Databeat 1 is transferred on the following clock cycle. In this example, the core deasserts its ready signal, s_axi_tx_tready , and no data is transferred until the next clock cycle when, again, the s_axi_tx_tready signal is asserted. Then the user application deasserts s_axi_tx_tvalid on the next clock cycle and no data is transferred until both signals are asserted.