Example D: Receiving a Multicycle UFC Message - 12.0 English

This Figure shows an Aurora 64B/66B core with an 8-byte interface receiving a 15-byte message. The resulting frame is two cycles long, with m_axi_ufc_rx_tkeep set to 8’hFF for the first cycle indicating that all bytes are valid and 8’hFE for the second cycle indicating that seven of the bytes are valid.

Figure 2-25: Receiving a Multi-Cycle UFC Message

X-Ref Target - Figure 2-25