FRAME_CHECK - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

This module is used to check the RX data integrity. As the FRAME_GEN module uses an LFSR with a known seed value, the same LFSR and seed value are used in the FRAME_CHECK module to compute the expected frame RX data. The received user data is validated against the expected data and any errors are reported as per the AXI4-Stream protocol. The FRAME_CHECK module is applicable to the AXI4-Stream data, UFC, NFC and USER-K interfaces.

The design can also be used as a reference for connecting the more complex interfaces on the Aurora 64B/66B core, such as the clocking interface.

When using the example design on a board, be sure to edit the <component name>_exdes file in the example_design subdirectory to supply the correct pins and clock constraints. Table: Example Design I/O Ports describes the ports available in the example design.

Table 5-1: Example Design I/O Ports

Port

Direction

Clock Domain

Description

rxn[0: m –1]

Input

Serial Clock

Negative differential serial data input pin.

rxp[0: m –1]

Input

Serial Clock

Positive differential serial data input pin.

txn[0: m –1]

Output

Serial Clock

Negative differential serial data output pin.

txp[0: m –1]

Output

Serial Clock

Positive differential serial data output pin.

reset

Input

user_clk

Reset signal for the example design.

< reference clock(s) >

Input

user_clk

The reference clocks for the Aurora 64B/66B core are brought to the top level of the example design. See Reference Clocks for FPGA Designs for details about the reference clocks.

< core error signals > (1)

Output

user_clk

The error signals from the Aurora 64B/66B core Status and Control interface are brought to the top level of the example design and registered.

< core channel up signals > (1)

Output

user_clk

The channel up status signals for the core are brought to the top level of the example design and registered.

< core lane up signals > (1)

Output

user_clk

The lane up status signals for the core are brought to the top level of the example design and registered. Cores have a lane up signal for each GTX and GTH transceiver they use.

pma_init

Input

init_clk

The reset signal for the PCS and PMA modules in the GTX and GTH transceivers is connected to the top level through a debouncer. The signal is debounced using the init_clk. See the Reset section in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for further details on GT RESET.

init_clk_p/

init_clk_n

Input

-

The init_clk signal is used to register and debounce the PMA_INIT signal. The init_clk signal must not come from a GTX or GTH transceiver, and should be set to a low rate, preferably lower than the reference clock. The init_clk port in the example design is differential-ended for UltraScale™ devices.

data_err_count[0:7]

Output

user_clk

Count of the number of frame data words received by the FRAME_CHECK that did not match the expected value.

ufc_err

Output

user_clk

Asserted (active-High) when UFC data words received by the FRAME_CHECK that did not match the expected value.

user_k_err

Output

user_clk

Asserted (active-High) when USER-K data words received by the FRAME_CHECK that did not match the expected value.

Notes:

1. See Status, Control and the Transceiver Interface for details.