• General-purpose data channels with throughput range from 500 Mb/s to over 400 Gb/s
• Supports up to 16 consecutively bonded 7 series GTX/GTH, UltraScale™ GTH/GTY or UltraScale+™ GTH/GTY or Versal® GTY/GTYP/GTM transceivers
• The GT subcore is also available outside the Aurora core
• Aurora 64B/66B protocol specification v1.3 compliant (64B/66B encoding)
• Low resource cost with very low (3%) transmission overhead
• Easy-to-use AXI4-Stream based framing and flow control interfaces
• Automatically initializes and maintains the channel
• Full-duplex or simplex operation
• 32-bit Cyclic Redundancy Check (CRC) for user data
• Added support for the Simplex Auto Link Recovery feature
• Supports RX polarity inversion
• Big endian/little endian AXI4-Stream user interface
• Fully compliant AXI4-Lite DRP interface
• Configurable DRP, INIT clock
• Single-ended or differential clocking options for GTREFCLK and core INIT_CLK
LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
Versal® ACAP, UltraScale+™, UltraScale ™ (2) , Zynq®-7000 SoC |
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Supported User Interfaces |
AXI4-Stream |
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Resources (3) |
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Provided with Core |
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Design Files |
Verilog |
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Example Design |
Verilog (4) |
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Test Bench |
Verilog |
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Constraints File |
Xilinx Design Constraints (XDC) |
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Simulation Model |
Source HDL with SecureIP transceiver simulation models |
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Supported
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N/A |
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Tested Design Flows (5) |
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Design Entry |
Vivado ® Design Suite |
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Simulation |
For supported simulators, see the
|
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 21263 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete list of supported devices and configurations, see the Vivado IP catalog and associated FPGA Datasheets. 2. For more information on supported device family, see References . 3. For more complete performance data, see Performance . 4. The IP core is delivered as Verilog source code. A mixed-language simulator is required for example design simulation because of subcore dependencies.
5.
For the supported versions of the tools, see the
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