Features - 12.0 English

Core Specifics

Supported Device Family ⁽¹⁾

Versal® ACAP, UltraScale+™,

UltraScale ™ ⁽²⁾ ,

Zynq®-7000 SoC

Virtex-7 ⁽²⁾ , Kintex-7 ⁽²⁾

Supported User Interfaces

AXI4-Stream

Resources ⁽³⁾

Performance and Resource Utilization web page

Provided with Core

Design Files

Verilog

Example Design

Verilog ⁽⁴⁾

Test Bench

Verilog

Constraints File

Xilinx Design Constraints (XDC)

Simulation Model

Source HDL with SecureIP transceiver simulation models

Supported
S/W Driver

N/A

Tested Design Flows ⁽⁵⁾

Design Entry

Vivado ® Design Suite

Simulation

For supported simulators, see the
Xilinx Design Tools: Release Notes Guide .

Synthesis

Vivado Synthesis

Support

Release Notes and Known Issues

Master Answer Record: 21263

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:

1. For a complete list of supported devices and configurations, see the Vivado IP catalog and associated FPGA Datasheets.

2. For more information on supported device family, see References .

3. For more complete performance data, see Performance .

4. The IP core is delivered as Verilog source code. A mixed-language simulator is required for example design simulation because of subcore dependencies.

5. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide .