The transceiver attributes play a vital role in the functionality of the Xilinx ® LogiCORE ™ IP Aurora 64B/66B core. Use the latest transceiver wizard to generate the transceiver wrapper file.
RECOMMENDED: Xilinx strongly recommends updating the transceiver wrapper file in the Vivado ® Design Suite tool releases when the transceiver wizard has been updated but the Aurora 64B/66B core has not.
1. Using the Vivado IP Catalog, run the latest version of the 7 series FPGAs Transceivers Wizard. Ensure the Component Name of the transceiver wizard matches the Component Name of the Aurora 64B/66B core.
2. Select the protocol template: Aurora 64B/66B .
3. Set the Line Rate for both the TX and RX transceivers based on the application requirement.
4. Select the Reference Clock from the drop-down menu for both the TX and RX transceivers based on the application requirement.
5. Select transceiver(s) and the clock source(s) based on the application requirement.
6. On Page 3, select External Data Width of the RX transceiver to be 32 Bits and Internal Data Width to be 32 bits. Ensure that the TX transceiver is configured with 64-bit external data width and 32-bit internal data width.
7. Keep all other settings as default.
8. Generate the core.
9. Replace the <user_component_name>_gtx.v file in the example_design/gt/ directory available in the Aurora 64B/66B core with the generated <user_component_name>_gt.v file generated from the 7 series FPGAs Transceivers Wizard.
Note: The UltraScale™ architecture Aurora 64B/66B core uses the hierarchical core calling method to call the UltraScale device GTWizard IP core. In this way, all the transceiver attributes, parameters, and required workarounds are up to date. Manual editing of the UltraScale device transceiver files are not required in most cases.