IP Facts - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID: PG074
Release Date: 2022-10-19
Version: 12.0 English

Aurora 64B/66B v12.0 LogiCORE IP Product Guide
IP Facts
Introduction
Features
Overview
Navigating Content by Design Process
Core Overview
Applications
Unsupported Features
Licensing and Ordering
Product Specification
Performance
Maximum Frequencies
Latency
Throughput
Resource Utilization
Port Descriptions
User Interface
Top‐Level Interface
Framing Interface
Transmitting Data
Aurora 64B/66B Frames
Example A: Simple Data Transfer
Example B: Data Transfer with Pause
Example C: Data Transfer with Clock Compensation
Receiving Data
Example A: Data Reception with Pause
Framing Efficiency
Streaming Interface
Transmitting and Receiving Data
Example A: TX Streaming Data Transfer
Example B: RX Streaming Data Transfer
Clock Interface
Flow Control Interface
Native Flow Control Interface
NFC Message in Default Mode
Example A: Transmitting an NFC Message
Example B: Receiving a Message with NFC Idles Inserted
User Flow Control Interface
Transmitting UFC Messages
Example A: Transmitting a Single-Cycle UFC Message
Example B: Transmitting a Multicycle UFC Message
Example C: Receiving a Single-Cycle UFC Message
Example D: Receiving a Multicycle UFC Message
USER-K Block Interface
Transmitting USER-K Blocks
Receiving USER-K Blocks
Status, Control and the Transceiver Interface
Status Control and Transceiver Ports
Error Signals in Aurora 64B/66B Cores
Initialization
Aurora 64B/66B Simplex Operation
Auto Link Recovery for Simplex
DRP Interface
Transceiver Debug Interface
CRC Interface
This Figure illustrates checking CRC at the core level. The figure shows 6 n bytes of received data of a frame. At the end of the frame, the core asserts m_axi_rx_tlast and crc_valid . In the same clock cycle the transmitted and computed CRCs are compared. If the values match, the crc_pass_fail_ n signal is asserted.
CRC Functionality for a GTY Transceiver Based Core
Generation of Aurora Without GT
Designing with the Core
General Design Guidelines
Keep It Registered
Recognize Timing Critical Signals
Make Only Allowed Modifications
Clocking
Aurora 64B/66B Clocking Architecture
Usage of BUFG in the Aurora 64B/66B Core
Reference Clocks for FPGA Designs
Reset and Power Down
Reset
Reset Sequence
Aurora 64B/66B Duplex
Aurora 64B/66B Duplex Power On Sequence
Aurora 64B/66B Duplex Normal Operation Reset Sequence
Reset Sequencing
Aurora 64B/66B Simplex
Aurora 64B/66B Simplex Power On Sequence
Aurora 64B/66B Simplex Normal Operation Reset Sequence
Aurora 64B/66B Simplex TX and RX
pma_init Staging in the Example Design
Reset Flow
Single Reset Use Cases
Use Case 1: reset_pb assertion in the duplex core
Use Case 2: pma_init Assertion in the Duplex Core
Use Case 3: Assertion of reset_pb in the Simplex Core
Power Down
Timing
Shared Logic
Using CRC
Hot Plug Logic
Clock Compensation Logic
Using Little Endian Support
Design Flow Steps
Customizing and Generating the Core
Core Options Tab for 7 Series FPGAs
Component Name
Line Rate
GT Reference Clock Frequency
INIT clk (MHz)
GT DRP clk (MHz)
Dataflow Mode
Generate Aurora without GT
Interface
Flow Control
USER K
Little Endian Support
CRC
DRP Mode
Vivado Lab Tools
Additional Transceiver Control and Status Ports
Core Options Tab for UltraScale Devices
Lanes
Starting GT Quad
GT Type
Starting GT Lane
GT Refclk Selection
Lanes
GT_TYPE
Lane Assignment
GT REFCLK1 and GT REFCLK2
Shared Logic
User Parameters
Xilinx IP - GT Quad Integration
Output Generation
Managing Shared Logic Files
GUI Options Tab for Versal Device
GT Type
Line Rate
Lanes
GT RefClk Req (MHz) & GT RefClk Actual (MHz)
PLL Requested
INIT clk (MHz)
Aurora IP generation Using "Block Automation" in IP Integrator
Constraining the Core
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
False Paths
Example Design
Simulation
Simulation Speed Up
Synthesis and Implementation
Example Design
Directory and File Contents
Quick Start Example Design
Generating the Core with Quick Start
Implementing the Example Design
Detailed Example Design
FRAME_GEN
FRAME_CHECK
Using Vivado Lab Tools
Implementing the Example Design
Hardware Reset FSM in the Example Design
Test Bench
Verification, Compliance, and Interoperability
Upgrading
Device Migration
Upgrading in the Vivado Design Suite
Shared Logic
Updates in the v9.0 Core
Migrating Legacy (LocalLink based) Aurora 64B/66B Cores to the AXI4-Stream Aurora 64B/66B Core
Prerequisites
Overview of Major Changes
Block Diagrams
Signal Changes
Migration Steps
Simulate the Core
Implement the Core
Integrate to an Existing LocalLink-based Aurora 64B/66B Design
Vivado IDE Changes
Limitations
Limitation 1:
Limitation 2:
Debugging
Finding Help on Xilinx.com
Documentation
Solution Centers
Answer Records
Technical Support
Vivado Design Suite Debug Feature
Simulation Debug
Lanes and Channel Do Not Come Up in Simulation
Channel Comes Up in Simulation But s_axi_tx_tready is Never Asserted (Never Goes High)
Bytes and Words Are Being Lost As They Travel Through the Aurora 64B/66B Channel
Problems While Compiling the Design
Next Step
Hardware Debug
Design Bring-Up on the KC705 Evaluation Board
Interface Debug
Generating a GT Wrapper File from the Transceiver Wizard
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

IP Facts

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