Initialization - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

The cores initialize automatically after power-up, reset, or hard error ( This Figure ). Core modules on each side of the channel perform the Aurora 64B/66B initialization procedure until the channel is ready for use. The lane_up bus indicates which lanes in the channel have finished the lane initialization portion of the procedure. The lane_up signal can be used to help debug equipment problems in a multi-lane channel. channel_up is asserted only after the core completes the entire initialization procedure.

Figure 2-35: Initialization Overview

X-Ref Target - Figure 2-35

pg074_Intialization-overview_x13040.jpg

Aurora 64B/66B cores can receive data before channel_up is asserted. Only the user interface m_axi_rx_tvalid signal should be used to qualify incoming data. Because no transmission can occur until after channel_up is asserted, channel_up can be inverted and used to reset modules that drive the TX side of a full-duplex channel. If user application modules need to be reset before data reception, an inverted lane_up signal can be used for this purpose. Data cannot be received until all of the lane_up signals are asserted.