Keep It Registered - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

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12.0 English

To simplify timing and increase system performance in an FPGA design, keep all inputs and outputs registered with a flip-flop between the user application and the core. While registering signals might not be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place-and-route the design.