Lanes and Channel Do Not Come Up in Simulation - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
Release Date
12.0 English

The quickest way to debug this issue is to view the signals from one of the GT transceiver instances that is not working.

Ensure that the reference clock and user clocks are all toggling.

Note: Only one of the reference clocks should be toggling, The rest are tied Low.

Check to see that recclk and txoutclk are toggling. If they are not toggling, it might be necessary to wait longer for the PMA to finish locking. Wait for lane up and channel up. It might be necessary to wait longer for simplex/7 series FPGA designs.

Ensure that txn and txp are toggling. If they are not, make sure to wait long enough (see the previous bulleted item) and make sure that another signal is not driving the txn / txp signal.

Check in the <user_component_name>_support module whether the pll/mmcm_not_locked signal and the reset signals are present in the design. If these are being held active, the Aurora 64B/66B module cannot initialize.

Ensure that the power_down signal is not being asserted.

Ensure that the txn and txp signals from each GTX or GTH transceiver are connected to the appropriate rxn and rxp signals from the corresponding GTX or GTH transceiver on the other side of the channel

Instantiate the "glbl" module and use it to drive the power_up reset at the beginning of the simulation to simulate the reset that occurs after configuration. Hold this reset for a few cycles. The following code can be used an example:

//Simulate the global reset that occurs after configuration at the beginning

//of the simulation.

assign glbl.GSR = gsr_r;

assign glbl.GTS = gts_r;



gts_r = 1'b0;

gsr_r = 1'b1;


gsr_r = 1'b0;


If you assert rx_reset while using Timer mode and simplex configuration, you should also assert tx_reset. This is to ensure that the core transmits the required initialization patterns for the rx_lane_up and rx_channel_up to come back. However, because of Simplex auto recovery logic, the RX could attain the rx_channel_up state if you wait for sufficient time. In this scenario, the TX transmits periodic patterns that aid in recovering links automatically.

If you are using a multilane channel, make sure all of the transceivers on each side of the channel are connected in the correct order.