Latency - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

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12.0 English

For a default single lane configuration, latency through an Aurora 64B/66B core is caused by pipeline delays through the protocol engine (PE) and through the GTX and GTH transceivers. The PE pipeline delay increases as the AXI4-Stream interface width increases. The transceiver delays are determined by the transceiver features.

This section outlines a method of measuring the latency for the Aurora 64B/66B core AXI4-Stream user interface in terms of user_clk cycles for Zynq®-7000, Virtex®-7, and Kintex®-7 device GTX, GTH transceiver-based designs and UltraScale™, UltraScale+ device GTH and GTY transceiver-based designs. For the purposes of illustrating latency, the Aurora 64B/66B modules are partitioned between logic in the GTX, GTH and GTY transceivers and protocol engine (PE) logic implemented in the FPGA.

This Figure illustrates the latency of the datapath.

Figure 2-2: Latency of the Datapath

X-Ref Target - Figure 2-2


Note: This Figure does not include the latency incurred due to the length of the serial connection between each side of the Aurora 64B/66B channel.

The latency must be measured from the rising edge of the transmitter user_clk at the first assertion of s_axi_tx_tvalid and s_axi_tx_tready to the rising edge of the receiver user_clk at the first assertion of m_axi_rx_tvalid . The following figure shows the transmitter and receiver path reference points between which the latency has been measured for the default core configuration.

Figure 2-3: Latency Waveform with Reference Points

X-Ref Target - Figure 2-3


The following table shows the maximum latency and the individual latency values of the contributing pipeline components for the default core configuration on 7 series GTX, GTH and UltraScale, UltraScale+ GTH transceiver based devices. Latency can vary with the addition of flow controls.

Table 2-1: Latency for the Default Aurora 64B/66B Core Configuration

Latency Component

user_clk Cycles




1 or 2

Clock Compensation


Maximum (total)

54 or 55

The pipeline delays are designed to maintain the clock speed.