Power Down - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

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12.0 English

When power_down is asserted, only the Aurora 64B/66B core logic is reset. This does not turn off the GTX, GTH or GTY transceivers used in the design.

CAUTION! Be careful when asserting this signal on cores that use tx_out_clk (see Reference Clocks for FPGA Designs ). tx_out_clk stops when the GTX, GTH and GTY transceivers are powered down. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] , UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 5] , UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 6] , and Versal ACAP GTY Transceivers Architecture Manual (AM002) [Ref 30] for power saving details.