The following figure shows a block diagram of the
Core Block Diagram
The major functional modules of the
An instance of the lane logic module drives each GT transceiver. This lane logic initializes each individual transceiver, handles the encoding and decoding of control characters, and performs error detection.
The global logic module in the core performs the channel bonding for channel initialization. During operation, the channel keeps track of the Not Ready idle characters defined by the
protocol and monitors all the lane logic modules for errors.
RX user interface:
The AXI4-Stream receive (RX) user interface moves data from the channel to the application and also performs flow control functions.
TX user interface:
The AXI4-Stream transmit (TX) user interface moves data from the application to the channel and also performs flow control TX functions. The standard clock compensation module is embedded inside the core. This module controls the periodic transmission of the clock compensation (CC) character.