Product Specification - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

The following figure shows a block diagram of the Aurora 64B/66B core.

Figure 2-1: Aurora 64B/66B Core Block Diagram

X-Ref Target - Figure 2-1

pg074_64b66b_core_block_diag_x13012.jpg

The major functional modules of the Aurora 64B/66B core are:

Lane logic: Each GT transceiver is driven by an instance of the lane logic module which initializes each individual transceiver, handles the encoding and decoding of control characters, and performs error detection.

Global logic: The global logic module in the core performs the channel bonding for channel initialization. During operation, the channel keeps track of the Not Ready idle characters defined by the Aurora 64B/66B protocol and monitors all the lane logic modules for errors.

RX user interface: The AXI4-Stream receive (RX) user interface moves data from the channel to the application and also performs flow control functions.

TX user interface: The AXI4-Stream transmit (TX) user interface moves data from the application to the channel and also performs flow control TX functions. The standard clock compensation module is embedded inside the core. This module controls periodic transmission of the clock compensation (CC) character.