Reference Clocks for FPGA Designs - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

Aurora 64B/66B cores require low-jitter reference clocks for generating and recovering high-speed serial clocks in the GTX, GTH or GTY transceivers. Each reference clock can be set to the reference clock input ports: gtxq / gthq/gtyq . Reference clocks should be driven with high-quality clock sources whenever possible to decrease jitter and prevent bit errors. DCMs should never be used to drive reference clocks, because they introduce too much jitter.

For UltraScale and UltraScale+ devices, the Xilinx implementation tools make necessary adjustments to the north-south routing and the pin swapping necessary to the GT transceiver clock inputs to route clocks from one quad to another, when required, based on the clock location constraints mentioned in example design xdc file.

The following rules must be observed when sharing a reference clock to ensure that jitter margins for high-speed designs are met:

In 7 series FPGAs, the total number of GTX or GTH transceiver quads sourced by an external clock pin pair must not exceed three quads (one quad above and one quad below), or 12 GTXE2_CHANNEL/GTHE2_CHANNEL transceivers. Designs in 7 series FPGAs with more than 12 transceivers or more than three quads should use multiple external clock pins. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] .

In UltraScale FPGAs, the total number of transceiver quads sourced by an external clock pin pair must not exceed five quads (two quads above and two quads below), or twenty GTHE3/GTHE4_CHANNEL transceivers. See the UltraScale FPGAs GTH Transceivers User Guide (UG576) [Ref 5] .

For GTY core configuration and line rate > 16.375G, the Aurora 64b66b core will default to active transceiver Quads GTREFCLK. Each Quads GT Refclk should be individually fed. For more details, see UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 6] . Manual editing of the transceiver attributes is not recommended but can be performed following the recommendations in the aforementioned GT user guides.

Clock relationship with the line rates in Aurora core are as follows .

Table 3-1: Clock Relationship with Line Rates in Aurora Core

Clock

Line Rate Description

TX/RXUSRCLK Rate

Line Rate / Internal Datapath Width. TX/RXUSRCLK2 Rate follows Table 3-10 of UG576/UG578

7 series devices and GTHE3/GTHE4 transceivers

TX_DATA_WIDTH is 64

TX_INT_DATAWIDTH, RX_DATA_WIDTH and RX_INT_DATAWIDTH are 32.

For GTYE3/GTYE4 transceivers

TX_DATA_WIDTH, TX_INT_DATAWIDTH,RX_DATA_WIDTH, RX_INT_DATAWIDTH are selected as 64.

Table 3-2: PLL and Corresponding Line Rate Selections

PLL Selection

Line Rates in Gbps

UltraScale

CPLL

<=8

QPLL1 or QPLL0 (if QPLL1 not available)

>8 and <=13

QPLL0 or QPLL1 (if QPLL0 not available)

>13 and <=16.375

QPLL1 or QPLL0 (if QPLL1 not available)

>16.375 and <=19.6

QPLL0

Other line rates

7 Series

CPLL

<8

QPLL

>8

The following table shows PLL and the corresponding line rate selections.